1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a plurality of memory cells divided and arranged in a plurality of memory mats.
2. Description of the Background Art
Semiconductor memory devices, for example, flash memories have been developed in which information can be stored by injecting electrons into or removing electrons from a floating gate (FG). A flash memory includes a memory cell having a floating gate, a control gate (CG), a source, a drain, and a well (substrate). In a memory cell, a threshold voltage is raised when electrons are injected into the floating gate, and the threshold voltage is lowered when electrons are removed from the floating gate. In general, the distribution of the lowest threshold voltage is called an erasure state of a memory cell, and the distribution of the threshold voltage higher than that of the erasure state is called a writing state of a memory cell. For example, when a memory cell stores two-bit data, the threshold voltage distribution of the lowest voltage corresponds to a logic level “11”, and this state is called an erasure state. Then, a writing operation is performed on a memory cell to drive the threshold voltage higher than that of the erasure state thereby achieving the threshold voltages corresponding to logic levels “10”, “01” and “00”, and this state is called a writing state. Furthermore, in a semiconductor memory device, for example, data write and data read are performed on a memory cell by charging/discharging a voltage supply line such as a bit line connected to the memory cell.
Here, in recent years, the area of a memory mat having memory cells arranged therein becomes larger with the increased memory capacity, and the length of a bit line connected to a memory cell is increased. With the increased length of a bit line, the wiring capacitance is increased so that it takes long time to charge/discharge the bit line. Therefore, the data read time and the data write time for a memory cell are inevitably increased.
In order to solve such a problem, for example, Japanese Patent Laying-Open No. 06-103789 (Patent Document 1) discloses a semiconductor memory device as follows. Specifically, a memory array is divided in two, and a sense amplifier is provided between the memory arrays. Such a configuration prevents the increased bit line length and thus the increased wiring capacitance.
Now, the sense amplifier detecting data stored in a memory cell is usually connected to an input/output circuit for outputting read data to the outside and inputting write data from the outside. Here, when the interconnection line between the sense amplifier and the input/output circuit is long, the data read time is increased because of a large wiring capacitance. Especially in a semiconductor memory device having a memory cell storing multi-bit data, the number of times of data transfers between the sense amplifier and the input/output circuit is large, so that the increase in data read time is outstanding.
However, in semiconductor memory devices according to Patent Document 1 and Japanese Patent Laying-Open Nos. 08-235878, 2004-318941 and 08-147990 (Patent Documents 2-4), no measures are taken against the increase in data read time resulting from the data transfers between the sense amplifier and the input/output circuit.